HD64F7045F28V Datasheet, PDF (79/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Table 1.7 Pin Functions (cont)
Classification Symbol
I/O
Bus control
CASL
O
(cont)
RDWR
O
AH
O
WRHH
O
(QFP-144)
WRHL
O
(QFP-144)
CASHH
O
(QFP-144)
CASHL
O
(QFP-144)
Bus control
TCLKA
I
multifunction
TCLKB
timer/pulse unit
TCLKC
TCLKD
TIOC0A
I/O
TIOC0B
TIOC0C
TIOC0D
TIOC1A
I/O
TIOC1B
TIOC2A
I/O
TIOC2B
Name
Lower column
address strobe
DRAM
read/write
Address hold
HH write
HL write
HH column
address strobe
HL column
address strobe
MTU timer
clock input
Function
Timing signal for DRAM column
address strobe.
Output when the lower 8 bits of
data are accessed.
DRAM write strobe signal.
Address hold timing signal for
devices using an address/data
multiplex bus.
Indicates the writing of bits 31 to
24 of external data.
Indicates the writing of bits 23 to
16 of external data.
Timing signal for DRAM column
address strobe. Output when bits
31 to 24 of data are accessed.
Timing signal for DRAM column
address strobe. Output when bits
23 to 16 of data are accessed.
Input pins for external clocks to
the MTU counter.
MTU input
capture/ output
compare
(channel 0)
Channel 0 input capture
input/output compare output/PWM
output pins.
MTU input
capture/output
compare
(channel 1)
MTU input
capture/output
compare
(channel 2)
Channel 1 input capture
input/output compare output/PWM
output pins.
Channel 2 input capture
input/output compare output/PWM
output pins.
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