HD64F7045F28V Datasheet, PDF (635/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

CK
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 17.4 CMF Set Timing
17.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1, or by a
clear signal after a DTC transfer. Figure 17.5 shows the timing when the CMF bit is cleared by the
CPU.
CMCSR write cycle
T₁
T₂
CK
CMF
Figure 17.5 Timing of CMF Clear by the CPU
595