HD64F7045F28V Datasheet, PDF (164/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
CP1
CP0
ID1
ID0 RW1 RW0 SZ1 SZ0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15–8—Reserved: These bits always read as 0. The write value should always be 0.
• Bits 7 and 6—CPU Cycle/Peripheral Cycle Select (CP1, CP0): These bits designate break
conditions for CPU cycles or peripheral cycles (DMA/DTC cycles).
Bit 7: CP1
0
1
Bit 6: CP0
0
1
0
1
Description
No user break interrupt occurs (initial value)
Break on CPU cycles
Break on peripheral cycles
Break on both CPU and peripheral cycles
• Bits 5 and 4—Instruction Fetch/Data Access Select (ID1, ID0): These bits select whether to
break on instruction fetch and/or data access cycles.
Bit 5: ID1
0
1
Bit 4: ID0
0
1
0
1
Description
No user break interrupt occurs (initial value)
Break on instruction fetch cycles
Break on data access cycles
Break on both instruction fetch and data access cycles
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