HD64F7045F28V Datasheet, PDF (189/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Register
information
start address
Memory space Memory space Memory space
DTMR
DTCRA
DTSAR
DTDAR
DTMR
DTCRA
DTIAR
DTSAR
DTDAR
DTMR
DTCRA
DTCRB
DTSAR
DTDAR
Register
information
Normal mode
Repeat mode Block transfer mode
Figure 8.5 DTC Register Information Placement in Memory Space
8.3.5 Normal Mode
Performs the transfer of one byte, one word, or one longword for each activation. The total
transfer count is 1 to 65536. An interrupt request is generated to the CPU when the transfer with
DTCRA = 1 ends. Transfers of a number of bytes specified by the SCI are possible.
Table 8.3 shows the register functions for normal mode.
Table 8.3 Normal Mode Register Functions
Register
DTMR
DTCRA
DTSAR
DTDAR
Function
Operation mode
control
Transfer count
Transfer source
address
Transfer destination
address
Values Written Back upon a
Transfer Information Write
When DTCRA
is other than 1
When DTCRA is 1
DTMR
DTMR
DTCRA – 1
Increment/decrement/
fixed
Increment/decrement/
fixed
DTCRA – 1 (= H'0000)
Increment/decrement/
fixed
Increment/decrement/
fixed
8.3.6 Repeat Mode
Performs the transfer of one byte, one word, or one longword for each activation. Either the
transfer source or transfer destination is designated as the repeat area.
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