HD64F7045F28V Datasheet, PDF (197/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Table 9.1 Register Configuration
Name
Abbreviation R/W
Cache control register CCR
R/W
Note: * Bits 15–5 are undefined.
Initial
Value
H'0000^*
Address
H'FFFF8740
Access Size
(Bits)
8, 16, 32
9.2 Register Explanation
9.2.1 Cache Control Register (CCR)
The cache control register (CCR) selects the cache enable/disable of each space.
The CCR is a 16-bit readable/writable register. It is initialized to H'0000 by power on resets, but is
not initialized by manual resets or standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: *
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
—
—
Initial value: *
*
R/W: R
R
Note: * Bits 15–5 are undefined.
5
4
3
2
1
0
—
CE
CE
CE
CE
CE
DRAM CS3 CS2 CS1 CS0
*
0
0
0
0
0
R
R/W R/W R/W R/W R/W
• Bits 15–5—Reserved: Reading these bits gives undefined values. The write value should
always be 0.
• Bit 4—DRAM Space Cache Enable (CEDRAM): Selects whether to use DRAM space as a
cache object (enable) or to exclude it (disable). A 0 disables, and a 1 enables such use.
Bit 4 (CEDRAM)
0
1
Description
DRAM space cache disabled (initial value)
DRAM space cache enabled
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