HD64F7045F28V Datasheet, PDF (652/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

• Bit 0—PA16 Mode (PA16MD): Selects the function of the PA16/AH pin.
Bit 0: PA16MD
0
1
Description
General input/output (PA16) (initial value)
Address hold output (AH) (PA16 in single chip mode)
18.3.4 Port A Control Registers L1, L2 (PACRL1 and PACRL2)
PACRL1 and PACRL2 are 16-bit read/write registers that select the functions of the least
significant sixteen multiplexed pins of port A. PACRL1 selects the function of the PA15/CK–
PA8/TCLKC/IRQ2 pins of port A; PACRL2 selects the function of the PA7/TCLKB/CS3–
PA0/RXD0 pins of port A.
Port A has bus control signals (RD, WRH, WRL, CS0–CS3, AH) and DMAC control signals
(DREQ0–DREQ1), but there are instances when the register settings that select these pin functions
will be ignored, depending on the operation mode. Refer to table 18.2, Pin Arrangement by Mode,
for details.
PACRL1 is initialized by external power-on reset to H'4000 in extended mode, and to H'0000 in
single chip mode. PACRL2 is initialized by external power-on reset to H'0000. Neither register is
initialized by manual resets, reset by WDT, standby mode, or sleep mode, so the previous data is
maintained.
Port A Control Register L1 (PACRL1):
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
— PA15MD — PA14MD — PA13MD — PA12MD
0
0(1)^*
0
0
0
0
0
0
R
R/W
R
R/W
R
R/W
R
R/W
Bit: 7
6
5
4
3
2
1
0
— PA11MD — PA10MD PA9MD1 PA9MD0 PA8MD1 PA8MD0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W
R
R/W R/W R/W R/W R/W
Note: * Bit 14 is initialized to 1 in extended mode.
• Bit 15—Reserved: This bit always reads as 0. The write value should always be 0.
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