HD64F7045F28V Datasheet, PDF (486/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

12.10 POE Register Descriptions
12.10.1 Input Level Control/Status Register (ICSR)
The input level control/status register (ICSR) is a 16-bit read/write register that selects the POE0–
POE3 pin input modes, controls the enable/prohibit of interrupts, and indicates status. If any of the
POE3F–POE0F bits are set to 1, the high current pins become high impedance state.
ICSR is initialized to H'0000 by power-on resets; however, it is not initialized for manual resets,
standby mode, or sleep mode, so the previous data is maintained.
Bit:
15
14
13
12
11
10
9
8
POE3F POE2F POE1F POE0F —
—
—
PIE
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)^* R/(W)^* R/(W)^* R/(W)^* R
R
R
R/W
Bit: 7
6
5
4
3
2
1
0
POE3M1 POE3M0 POE2M1 POE2M0 POE1M1 POE1M0 POE0M1 POE0M0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Note: * Only 0 writes are possible to clear the flags.
• Bit 15—POE3 Flag (POE3F): This flag indicates that a high impedance request has been input
to the POE3 pin.
Bit 15: POE3F
0
1
Description
Clear condition: By writing 0 to POE3F after reading a POE3F = 1
(initial value)
Set condition: When the input set by ICSR bits 7 and 6 occurs at
the POE3 pin
• Bit 14—POE2 Flag (POE2F): This flag indicates that a high impedance request has been input
to the POE2 pin.
Bit 14: POE2F
0
1
Description
Clear condition: By writing 0 to POE2F after reading a POE2F = 1
(initial value)
Set condition: When the input set by ICSR bits 5 and 4 occurs at
the POE2 pin
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