HD64F7045F28V Datasheet, PDF (275/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

11.3.4 DMA Transfer Types
The DMAC supports the transfers shown in table 11.5. It can operate in the single address mode,
in which either the transfer source or destination is accessed using an acknowledge signal, or dual
access mode, in which both the transfer source and destination addresses are output. The dual
access mode consists of a direct address mode, in which the output address value is the object of a
direct data transfer, and an indirect address mode, in which the output address value is not the
object of the data transfer, but the value stored at the output address becomes the transfer object
address. The actual transfer operation timing varies with the bus mode. The DMAC has two bus
modes: cycle-steal mode and burst mode.
Table 11.5 Supported DMA Transfers
Destination
Source
Memory-
Mapped
External Device External External On-Chip
with DACK
Memory Device Memory
On-Chip
Peripheral
Module
External device with DACK Not available Single Single Not available Not available
External memory
Single
Dual
Dual Dual
Dual
Memory-mapped external Single
device
Dual
Dual Dual
Dual
On-chip memory
Not available Dual
Dual Dual
Dual
On-chip peripheral module Not available Dual
Dual Dual
Dual
Notes: 1. Single: Single address mode
2. Dual: Dual address mode; includes both direct address mode and indirect address
mode.
11.3.5 Address Modes
Single Address Mode: In the single address mode, both the transfer source and destination are
external; one (selectable) is accessed by a DACK signal while the other is accessed by an address.
In this mode, the DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a
transfer request acknowledge DACK signal to one external device to access it while outputting an
address to the other end of the transfer. Figure 11.5 shows an example of a transfer between an
external memory and an external device with DACK in which the external device outputs data to
the data bus while that data is written in external memory in the same bus cycle.
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