HD64F7045F28V Datasheet, PDF (417/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

12.5 Interrupts
12.5.1 Interrupt Sources and Priority Ranking
The MTU has three interrupt sources: TGR register compare-match/input captures, TCNT counter
overflows and TCNT counter underflows. Because each of these three types of interrupts are
allocated its own dedicated status flag and enable/disable bit, the issuing of interrupt request
signals to the interrupt controller can be independently enabled or disabled.
When an interrupt source is generated, the corresponding status flag in the timer status register
(TSR) is set to 1. If the corresponding enable/disable bit in the timer input enable register (TIER)
is set to 1 at this time, the MTU makes an interrupt request of the interrupt controller. The
interrupt request is canceled by clearing the status flag to 0.
The channel priority order can be changed with the interrupt controller. The priority ranking
within a channel is fixed. For more information, see section 6, Interrupt Controller (INTC).
Table 12.17 lists the MTU interrupt sources.
Input Capture/Compare Match Interrupts: If the TGIE bit of the timer input enable register
(TIER) is already set to 1 when the TGF flag in the timer status register (TSR) is set to 1 by a TGR
register input capture/compare-match of any channel, an interrupt request is sent to the interrupt
controller. The interrupt request is canceled by clearing the TGF flag to 0. The MTU has 16 input
capture/compare-match interrupts; four each for channels 0, 3, and 4, and two each for channels 1
and 2.
Overflow Interrupts: If the TCIEV bit of the TIER is already set to 1 when the TCFV flag in the
TSR is set to 1 by a TCNT counter overflow of any channel, an interrupt request is sent to the
interrupt controller. The interrupt request is canceled by clearing the TCFV flag to 0. The MTU
has five overflow interrupts, one for each channel.
Underflow Interrupts: If the TCIEU bit of the TIER is already set to 1 when the TCFU flag in
the TSR is set to 1 by a TCNT counter underflow of any channel, an interrupt request is sent to the
interrupt controller. The interrupt request is canceled by clearing the TCFU flag to 0. The MTU
has two underflow interrupts, one each for channels 1 and 2.
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