HD64F7045F28V Datasheet, PDF (434/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

12.7.6 Contention between TGR Read and Input Capture
If an input capture signal is issued in the T₁ state of the TGR read cycle, the read data is that after
input capture transfer (figure 12.81).
φ
Address
Read signal
Input capture
signal
TGR
TGR read cycle
T₁
T₂
TGR
address
X
M
Internal data
M
bus
Figure 12.81 TGR Read and Input Capture Contention
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