HD64F7045F28V Datasheet, PDF (637/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

17.5.2 Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T₂ state of the CMCNT counter word write cycle, the counter
write has priority, so no increment occurs. Figure 17.7 shows the timing.
CMCNT write cycle
T₁
T₂
CK
Address
CMCNT
Internal
write signal
Compare
match signal
CMCNT
N
M
CMCNT write data
Figure 17.7 CMCNT Word Write and Increment Contention
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