HD64F7045F28V Datasheet, PDF (346/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

• Bits 3–0—I/O Control C3–C0 (IOC3–IOC0): These bits set the TGR4C register function.
Bit 3: Bit 2: Bit 1: Bit 0:
IOC3 IOC2 IOC1 IOC0 Description
0
0
0
0
TGR4C
Output disabled (initial value)
1
is an
Initial
Output 0 on compare-match
1
0
output
output
Output 1 on compare-match
1
compare is 0
Toggle output on compare-match
1
0
0
register
Output disabled
1
Initial
Output 0 on compare-match
1
0
output
Output 1 on compare-match
1
is 1
Toggle output on compare-match
1
0
0
0
TGR4C
Capture
Input capture on rising edge
1
is an
input source
Input capture on falling edge
1
0
input
is the
Input capture on both edges
1
capture
TIOC4C pin
1
0
0
register
Input capture on rising edge
1
Input capture on falling edge
1
0
Input capture on both edges
1
Note: When the BFA bit of TMDR4 is set to 1 and TGR4C is being used as a buffer register, these
settings become ineffective and input capture/output compares do not occur.
12.2.4 Timer Interrupt Enable Register (TIER)
The TIER is an 8-bit register that controls the enable/disable of interrupt requests for each channel.
The MTU has five TIER registers, one each for channel. TIER is initialized to H'40 by a reset or
by standby mode.
Channel 0: TIER0:
Bit: 7
6
TTGE
—
Initial value: 0
1
R/W: R/W
R
5
4
3
2
1
0
— TCIEV TGIED TGIEC TGIEB TGIEA
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W
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