HD64F7045F28V Datasheet, PDF (498/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

13.2.2 Timer Control/Status Register (TCSR)
The timer control/status register (TCSR) is an 8-bit read/write register. (The TCSR differs from
other registers in that it is more difficult to write to. See section 13.2.4, Register Access, for
details.) Its functions include selecting the timer mode and clock source.
Bits 7–5 are initialized to 000 by a power-on reset or in standby mode. Bits 2–0 are initialized to
000 by a power-on reset, but retain their values in the standby mode. These bits are not initialized
by a manual reset from an external source (MRES), but are initialized by a manual reset from the
WDT.
Bit: 7
6
5
4
OVF WT/IT TME
—
Initial value: 0
0
0
1
R/W: R/(W) R/W R/W
R
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
R
R/W R/W R/W
• Bit 7—Overflow Flag (OVF): Indicates that the TCNT has overflowed from H'FF to H'00 in
the interval timer mode. It is not set in the watchdog timer mode.
Bit 7: OVF
0
1
Description
No overflow of TCNT in interval timer mode (initial value)
Cleared by reading OVF, then writing 0 in OVF
TCNT overflow in the interval timer mode
• Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer. When the TCNT overflows, the WDT either generates an interval timer
interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected.
Bit 6: WT/IT
0
1
Description
Interval timer mode: interval timer interrupt request to the CPU when
TCNT overflows (initial value)
Watchdog timer mode: WDTOVF signal output externally when TCNT
overflows. (Section 13.2.3, Reset Control/Status Register (RSTCSR),
describes in detail what happens when TCNT overflows in the watchdog
timer mode.)
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