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HD64F7045F28V Datasheet, PDF (608/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series
16.1.2 Block Diagram
Figure 16.1 is the block diagram of the mid-speed A/D converter.
AVCC, AVref and AVSS pins of both A/D are common in LSI.
A/D0
Module data bus
AVcc
AVref
(Only with 144 pin)
AVss
10-bit D/A
AN0
+
AN1
−
AN2
Comparator
AN3
Sample & hold circuit
Control circuit
Port MTU
trigger trigger
Logical
sum
Interrupt
signal ADI0
(DTC)
A/D1
Module data bus
AVcc
(Only with 144 pin)
AVref
AVss
10-bit D/A
AN4
+
AN5
−
AN6
Comparator
Control circuit
AN7
Sample & hold circuit
Interrupt
signal ADI1
(DMAC)
Figure 16.1 Mid-Speed A/D Converter Block Diagram
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