HD64F7045F28V Datasheet, PDF (207/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

10.1.5 Address Map
Figure 10.2 shows the address format used by the SH7040 Series.
A31–A24
A23, A22 A21
A0
Output address:
Output from the address pins
CS space selection:
Decoded, outputs CS0 to CS3 when A31 to A24 = 00000000
Space selection:
Not output externally; used to select the type of space
On-chip ROM space or CS space when 00000000 (H'00)
DRAM space when 00000001 (H'01)
Reserved (do not access) when 00000010 to 11111110 (H'02 to H'FE)
On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
Figure 10.2 Address Format
This LSI uses 32-bit addresses:
• A31–A24 are used to select the type of space and are not output externally.
• Bits A23 and A22 are decoded and output as chip select signals (CS0–CS3) for the
corresponding areas when bits A31–A24 are 00000000.
• A21–A0 are output externally.
Table 10.3 shows an address map for on-chip ROM effective mode. Table 10.4 shows an address
map for on-chip ROM ineffective mode.
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