HD64F7045F28V Datasheet, PDF (735/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

22.5.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a power-on reset and standby mode, when a high level is input to the FWP
pin, and when a low level is input to the FWP pin and the SWE bit in FLMCR1 is not set. When a
bit in EBR1 is set to 1, the corresponding block can be erased. Other blocks are erase-protected.
Only one of the bits of EBR1 and EBR2 combined can be set. Do not set more than one bit. If
more than one bit is set, writes to bits ESU1, ESU2, E1, and E2 will be invalid. When on-chip
flash memory is disabled, a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 22.4.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
EB3 EB2 EB1 EB0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
22.5.4 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a power-on reset and standby mode, when a high level is input to the FWP
pin, and when a low level is input to the FWP pin and the SWE bit in FLMCR1 is not set. When a
bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected.
When on-chip flash memory is disabled, a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 22.4.
Bit: 7
6
5
4
3
2
1
0
EB11 EB10 EB9 EB8 EB7 EB6 EB5 EB4
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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