HD64F7045F28V Datasheet, PDF (435/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

12.7.7 Contention between TGR Write and Input Capture
If an input capture signal is issued in the T₂ state of the TGR read cycle, input capture has priority,
and TGR write does not occur (figure 12.82).
TGR write cycle
T₁
T₂
φ
Address
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 12.82 TGR Write and Input Capture Contention
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