HD64F7045F28V Datasheet, PDF (432/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

12.7.5 Contention between Buffer Register Write and Compare Match
If a compare-match occurs in the T₂ state of the TGR write cycle, data is transferred by the buffer
operation from the buffer register to the TGR. Data to be transferred differs depending on channels
0 and 3 and 4: data on channel 0 is that after write, and on channels 3 and 4, before write (figures
12.79 and 12.80).
TGR write cycle
T₁
T₂
φ
Address
Write signal
Compare
match
signal
Compare
match buffer
signal
Buffer
register
Buffer register
address
Buffer register write data
N
M
TGR
M
Figure 12.79 TGR Write and Compare-Match Contention (Channel 0)
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