HD64F7045F28V Datasheet, PDF (370/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Input Capture Operation: Figure 12.14 shows input capture. The falling edge of TIOCB and
both edges of TIOCA are selected as input capture input edges. In the example, TCNT is set to
clear at the input capture of the TGRB register.
TCNT value
H'0180
H'0160
H'0010
H'0005
H'0000
TIOCA
Counter cleared
by TIOCB input
(falling edge)
Time
TGRA
TIOCB
H'0005
H'0160
H'0010
TGRB
H'0180
Figure 12.14 Input Capture Operation
12.4.3 Synchronous Operation
In the synchronizing mode, two or more timer counters can be rewritten simultaneously
(synchronized preset). Multiple timer counters can also be cleared simultaneously using TCR
settings (synchronized clear).
The synchronizing mode can increase the number of TGR registers for a single time base. All five
channels can be set for synchronous operation.
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