HD64F7045F28V Datasheet, PDF (589/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

ADF
ADST
Set to 1 by software
Channel 0 ^{Conversion standby}
Automatic clear
Channel 1
Conversion
standby
Sampling 1
A/D
conversion 1
Conversion
standby
Channel 2 Conversion standby
Channel 3 Conversion standby
ADDRA
ADDRB
ADDRC
Conversion result 1
ADDRD
Figure 15.4 A/D Converter Operation Example (Select-Single Mode)
15.4.2 Select-Scan Mode
Choose select-scan mode when doing repeated A/D conversions for one channel. This is useful
when doing continuous monitoring of the analog input of one channel.
When the ADST bit is set to 1, A/D conversion is started according to the designated conversion
start conditions. The ADST bit is held to 1 until 0 cleared by software. A/D conversion for the
selected input channel is repeated during that interval.
The ADF flag is set to 1 at the end of the first conversion. At this point, if the ADIE bit is set, an
ADI interrupt request is issued, and the A/D converter is halted. With the A/D converter in stop
mode due to an ADI interrupt request, conversion is restarted when the ADF flag is cleared to 0.
The ADF flag is cleared by reading the ADCSR then writing a 0.
Figure 15.5 shows an example of operation in the select-scan mode when AN1 is selected.
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