HD64F7045F28V Datasheet, PDF (638/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

17.5.3 Contention between CMCNT Byte Write and Incrementation
If an increment occurs during the T₂ state of the CMCNT byte write cycle, the counter write has
priority, so no increment of the write data results on the writing side. The byte data on the side not
performing the writing is also not incremented, so the contents are those before the write.
Figure 17.8 shows the timing when an increment occurs during the T₂ state of the CMCNTH write
cycle.
CMCNT write cycle
T₁
T₂
CK
Address
CMCNTH
Internal
write signal
CMCNT
input clock
CMCNTH
N
CMCNTL
X
M
CMCNTH write data
X
Figure 17.8 CMCNT Byte Write and Increment Contention
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