HD64F7045F28V Datasheet, PDF (377/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Cascade Connection Operation Examples—Phase Counting Mode: Figure 12.23 shows an
example of operation when the TCNT1 counter is set to count on TCNT2 overflow/underflow and
channel 2 is set to phase counting mode.
The TCNT1 counter increments with a TCNT2 counter overflow and decrements with a TCNT2
underflow.
TCLKC
TCLKD
TCNT2
FFFD FFFE FFFF 0000 0001
0002
0001 0000 FFFF
TCNT1
0000
0001
0000
Figure 12.23 Cascade Connection Operation Example (Phase Counting Mode)
12.4.6 PWM Mode
PWM mode outputs the various PWM waveforms from output pins. Output levels of 0 output, 1
output, or toggle output can be selected as the output level for the compare-match of each TGR.
A period can be set for a register by using the TGR compare-match as a counter clear source. All
five channels can be independently set to PWM mode. Synchronous operation is also possible.
There are two PWM modes:
• PWM mode 1
Generates PWM output using the TGRA and TGRB registers, and TGRC and TGRD registers
as pairs. The initial output values are those established in the TGRA and TGRC registers.
When the values set in TGR registers being used as a pair are equal, output values will not
change even if a compare-match occurs.
A maximum of 8-phase PWM output is possible for PWM mode 1.
• PWM mode 2
Generates PWM output using one TGR register as a period register and another as a duty cycle
register. The output value of each pin upon a counter clear is the initial value established by the
TIOR register. When the values set in the period register and duty register are equal, output
values will not change even if a compare-match occurs. PWM mode 2 can be set only for
channels 0, 1, and 2.
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