HD64F7045F28V Datasheet, PDF (636/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

17.5 Notes on Use
Take care that the contentions described in sections 17.5.1–17.5.3 do not arise during CMT
operation.
17.5.1 Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T₂ state of the CMCNT counter write cycle, the
CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure
17.6 shows the timing.
CMCNT write cycle
T₁
T₂
CK
Address
CMCNT
Internal
write signal
Compare
match signal
CMCNT
N
H'0000
Figure 17.6 CMCNT Write and Compare Match Contention
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