HD64F7045F28V Datasheet, PDF (436/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

12.7.8 Contention between Buffer Register Write and Input Capture
If an input capture signal is issued in the T₂ state of the buffer write cycle, write to the buffer
register does not occur, and buffer operation takes priority (figure 12.83).
φ
Address
Write signal
Input capture
signal
TCNT
Buffer register write cycle
T₁
T₂
Buffer register
address
N
TGR
M
N
Buffer
register
M
Figure 12.83 Buffer Register Write and Input Capture Contention
396