HD64F7045F28V Datasheet, PDF (107/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Table 2.13 Arithmetic Operation Instructions (cont)
Instruction
Instruction Code
Operation
Execu-
tion
Cycles T Bit
SUB
Rm,Rn
0011nnnnmmmm1000 Rn–Rm → Rn
1
—
SUBC Rm,Rn
0011nnnnmmmm1010 Rn–Rm–T → Rn,
1
Borrow
Borrow → T
SUBV Rm,Rn
0011nnnnmmmm1011
Rn–Rm → Rn,
Underflow → T
1
Overflow
Note: * The normal minimum number of execution cycles. (The number in parentheses is the
number of cycles when there is contention with following instructions.)
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