HD64F7045F28V Datasheet, PDF (512/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

14.2 Register Descriptions
14.2.1 Receive Shift Register (RSR)
The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into the
RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte
has been received, it is automatically transferred to the RDR.
The CPU cannot read or write the RSR directly.
Bit: 7
6
5
4
3
2
1
0
R/W: —
—
—
—
—
—
—
—
14.2.2 Receive Data Register (RDR)
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one
byte of serial data by moving the received data from the receive shift register (RSR) into the RDR
for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI
to receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H'00 by a power-on reset or in
standby mode. Manual reset does not initialize RDR.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
14.2.3 Transmit Shift Register (TSR)
The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the
transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB
(bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data
from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1,
however, the SCI does not load the TDR contents into the TSR.
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