HD64F7045F28V Datasheet, PDF (439/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

12.7.11 Counter Value during Complementary PWM Mode Stop
When counting operation is suspended with TCNT3 and TCNT4 in complementary PWM mode,
TCNT3 has the timer dead time register (TDDR) value, and TCNT4 is held at H'0000.
When restarting complementary PWM mode, counting begins automatically from the initialized
state (figure 12.86).
When counting begins in another operating mode, be sure that TCNT3 and TCNT4 are set to the
initial values.
TGR3A
TCDR
TCNT3
TCNT4
TDDR
H'0000
Complementary PWM
mode operation
Complementary PWM
mode operation
Counter
Complementary
operation stop PMW restart
Figure 12.86 Counter Value during Complementary PWM Mode Stop
12.7.12 Buffer Operation Setting in Complementary PWM Mode
In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting
register (TGR3A), PWM carrier cycle setting register (TCDR) and duty setting registers (TGR3B,
TRG4A, and TGR4B).
In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit
settings BFA and BFB of TMDR3. When TMDR3’s BFA bit is set to 1, TGR3C functions as a
buffer register for TGR3A. At the same time, TGR4C functions as the buffer register for TRG4A,
while the TCBR functions as the TCDR’s buffer register.
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