HD64F7045F28V Datasheet, PDF (387/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

input clock is used as the TGR0B register input capture source, and a pulse width of four times the
2-phase encoder pulse is detected.
The channel 1 TGR1A and TGR1B registers are set for the input capture function, the channel 0
TGR0A and TGR0C register compare-match is used as an input capture source, and all of the
control period increment and decrement values are stored.
TCLKA
TCLKB
Edge
detection
circuit
Channel 1
TCNT1
TGR1A (speed
period capture)
TGR1B (position
period capture)
TCNT0
TGR0A (speed
+
control period)
–
TGR0C (position
+
control period)
–
TGR0B (pulse
width capture)
TGR0D (buffer
operation)
Channel 0
Figure 12.34 Phase Count Mode Application Example
347