HD64F7045F28V Datasheet, PDF (205/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

10.1.3 Pin Configuration
Table 10.1 shows the bus state controller pin configuration.
Table 10.1 Pin Configuration
Signal
A21–A0
D31–D0
CS0–
CS3
RD
WRHH
WRHL
WRH
WRL
RDWR
RAS
CASHH
CASHL
CASH
CASL
AH
WAIT
BREQ
BACK
I/O Description
O Address output (A21–A18 will become input ports with power-on reset)
I/O 32-bit data bus. D15-D0 are address output and data I/O during address/data
multiplex I/O.
O Chip select
O Strobe that indicates the read cycle for ordinary space/multiplex I/O. Also
output during DRAM access.
O Strobe that indicates a write cycle to the most significant byte (D31–D24) for
ordinary space/multiplex I/O. Also output during DRAM access.
O Strobe that indicates a write cycle to the 2nd byte (D23–D16) for ordinary
space/multiplex I/O. Also output during DRAM access.
O Strobe that indicates a write cycle to the 3rd byte (D15–D8) for ordinary
space/multiplex I/O. Also output during DRAM access.
O Strobe that indicates a write cycle to the least significant byte (D7–D0) for
ordinary space/multiplex I/O. Also output during DRAM access.
O Strobe indicating a write cycle to DRAM (used for DRAM space)
O RAS signal for DRAM (used for DRAM space)
O CAS signal when accessing the most significant byte (D31–D24) of DRAM
(used for DRAM space)
O CAS signal when accessing the 2nd byte (D23–D16) of DRAM (used for DRAM
space)
O CAS signal when accessing the 3rd byte (D15–D8) of DRAM (used for DRAM
space)
O CAS signal when accessing the least significant byte (D7–D0) of DRAM (used
for DRAM space)
O Signal to hold the address during address/data multiplex
I Wait state request signal
I Bus release request input
O Bus use enable output
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