HD64F7045F28V Datasheet, PDF (620/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

16.4.3 Input Sampling and A/D Conversion Time
The mid-speed A/D converter is equipped with a sample and hold circuit. The mid-speed A/D
converter samples input after t_D hours has elapsed since setting the ADST bit of the A/D
control/status register (ADCSR) to 1, then begins conversion. The A/D conversion timing is
shown in table 16.4.
The A/D conversion time, as shown in figure 16.5, includes both t_D and input sampling time. Here,
t_D is determined by the write timing to ADCSR and is not constant. Thus the conversion time
changes in the range shown in table 16.4.
The conversion time shown in table 16.4 is the time for the first conversion. For the second
conversion and after, the time will be 256 state (fixed) for CKS=0 and 128 state (fixed) for
CKS=1.
(1)
CK
Address
(2)
Write signal
Input sampling
timing
ADF
t_D
< Key>
(1): Write cycle of ADCSR
(2): Address of ADCSR
t _SPL
t _CONV
t_D: A/D conversion start delay time
t_SPL: Input sampling time
t_CONV: A/D conversion time
Figure 16.5 A/D Conversion Timing
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