HD64F7045F28V Datasheet, PDF (259/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
…
…
Initial value: —
—
—
…
R/W: R/W R/W R/W
…
…
2
1
0
…
…
—
—
—
…
R/W R/W R/W
11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify
the destination address of a DMA transfer. These registers have a count function, and during a
DMA transfer, they indicate the next destination address. In single-address mode, DAR values are
ignored when a device with DACK has been specified as the transfer destination.
Specify a 16-bit or 32-bit boundary address when doing 16-bit or 32-bit data transfers. Operation
cannot be guaranteed on any other address. The initial value after power-on resets or in software
standby mode, is undefined. These registers are not initialized with manual reset.
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
…
…
Initial value: —
—
—
…
R/W: R/W R/W R/W
…
…
2
1
0
…
…
—
—
—
…
R/W R/W R/W
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