HD64F7045F28V Datasheet, PDF (195/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Section 9 Cache Memory (CAC)
9.1 Overview
The LSI has an on-chip cache memory (CAC) with 1 kbyte of cache data and a 256-entry cache
tag. The cache data and cache tag space can be used as on-chip RAM space when the cache is not
being used.
9.1.1 Features
The CAC has the following features. The cache tag and cache data configuration is shown in
figure 9.1.
• 1-kbyte capacity
• External memory (CS space and DRAM space) instruction code and PC relative data caching
• 256 entry cache tag (tag address 15 bits)
• 4-byte line length
• Direct map replacement algorithm
• Valid flag (1 bit) included for purges
15
8
2
CPU Tag
Entry
address address address ^Offset
Valid bit (1 bit)
Cache tag
Tag address (15 bits)
Cache data
Data (32 bits)
256 entries
CMP
Data bus
Hit signal
Figure 9.1 Cache Tag and Cache Data Configuration
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