HD64F7045F28V Datasheet, PDF (255/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

11.1.2 Block Diagram
Figure 11.1 is a block diagram of the DMAC.
On-chip ROM
On-chip RAM
On-chip
peripheral
module
DREQ0, DREQ1
MTU
SCI0, SCI1
A/D converter^*
DEIn
DACK0, DACK1
DRAK0, DRAK1
External
ROM
External
RAM
External I/O
(memory
mapped)
External I/O
(with
acknowledge)
DMAC module
Circuit
control
SARn
Register
control
Activation
control
DARn
DMATCRn
CHCRn
Request
priority
control
DMAOR
Bus interface
Bus state
controller
SARn: DMAC source address register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
DMAOR: DMAC operation register
n: 0, 1, 2, 3
Note: * A/D1 for A mask and A/D for others
Figure 11.1 DMAC Block Diagram
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