HD64F7045F28V Datasheet, PDF (210/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Bit: 15
14
13
12
11
10
9
8
—
—
MTU
—
—
—
—
IOE
RWE
Initial value: 0
0
1
0
0
0
0
0
R/W: R
R
R/W
R
R
R
R
R/W
Bit:
Initial value:
R/W:
7
A3LG
0
R/W
6
A2LG
0
R/W
5
A1LG
0
R/W
4
A0LG
0
R/W
3
A3SZ
1
R/W
2
A2SZ
1
R/W
1
A1SZ
1
R/W
0
A0SZ
1
R/W
• Bits 15, 14, 12–9—Reserved: These bits always read as 0. The write value should always be 0.
• Bit 13—MTU Read/Write Enable (MTURWE): When this bit is 1, MTU control register
access is enabled. See section 12, Multifunction Timer Pulse Unit (MTU), for details.
Bit 13 (MTURWE)
0
1
Description
MTU control register access is disabled
MTU control register access is enabled (initial value)
• Bit 8—Multiplex I/O Enable (IOE): Selects the use of CS3 space as ordinary space or
address/data multiplex I/O space. A 0 selects ordinary space and a 1 selects address/data
multiplex I/O space. When address/data multiplex I/O space is selected, the address and data
are multiplexed and output from the data bus. When CS3 space is an address/data multiplex
I/O space, bus size is decided by the A14 bit (A14 = 0: 8 bit, A14 = 1: 16 bit).
Bit 8 (IOE)
0
1
Description
CS3 space is ordinary space (initial value)
CS3 space is address/data multiplex I/O space
• Bit 7—CS3 Space Long Size Specification (A3LG): Specifies the CS3 space bus size. This is
effective only when CS3 space is ordinary space. When CS3 space is an address/data multiplex
I/O space, bus size is decided by the A14 bit.
Bit 7 (A3LG)
0
1
Description
According to the A3SZ bit specified value (initial value)
Longword (32 bit) size
170