HD64F7045F28V Datasheet, PDF (447/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

12.7.16 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 12.93 shows the operation timing when a TGR compare-match is specified as the clearing
source, and H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
Counter clear
signal
H'FFFF
H'0000
TGF flag
TCFV flag
Disabled
Figure 12.93 Contention between Overflow and Counter Clearing
407