HD64F7045F28V Datasheet, PDF (430/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

12.7.3 Contention between TCNT Write and Clear
If a counter clear signal is issued in the T₂ state during the TCNT write cycle, TCNT clearing has
priority, and TCNT write is not conducted (figure 12.77).
φ
Address
Write signal
Counter
clear signal
TCNT
TCNT write cycle
T₁
T₂
TCNT address
N
H'0000
Figure 12.77 TCNT Write and Clear Contention
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