HD64F7045F28V Datasheet, PDF (373/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

12.4.4 Buffer Operation
Buffer operation is a function of channels 0, 3, and 4. TGRC and TGRD can be used as buffer
registers. Table 12.5 shows the register combinations for buffer operation.
Table 12.5 Register Combinations
Channel
0
3
4
General Register
TGR0A
TGR0B
TGR3A
TGR3B
TGR4A
TGR4B
Buffer Register
TGR0C
TGR0D
TGR3C
TGR3D
TGR4C
TGR4D
The buffer operation differs, depending on whether the TGR has been set as an input capture
register or an output compare register.
When TGR Is an Output Compare Register: When a compare-match occurs, the corresponding
channel buffer register value is transferred to the general register. Figure 12.17 shows an example.
Compare match signal
Buffer
register
General
register
Comparator
TCNT
Figure 12.17 Compare Match Buffer Operation
When TGR Is an Input Capture Register: When an input capture occurs, the timer counter
(TCNT) value is transferred to the general register (TGR), and the value that had been held up to
that time in the TGR is transferred to the buffer register (figure 12.18).
Input capture signal
Buffer
register
General
register
Figure 12.18 Input Capture Buffer Operation
TCNT
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