HD64F7045F28V Datasheet, PDF (290/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

Figures 11.17 and 11.18 show cycle steal mode and single address mode. In this case, transfer
begins at earliest three cycles after the first DREQ sampling. The second sampling begins from the
start of the transfer one bus cycle before the start of the first DMAC transfer. In single address
mode, the DACK signal is output during the DMAC transfer period.
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