HD64F7045F28V Datasheet, PDF (202/925 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7040 Series

CK
Internal
address
Address
RAS
CASxx
Data
Miss-hit
Idle cycle
ROW
Idle cycle
COLUMN
RAS assert extension
Idle cycle
Figure 9.7 Cache Fill Timing in Case of Non-Consecutive Cache Miss from DRAM Space
(Normal Mode, TPC = 0, RCD = 0, No Wait)
DRAM access
CS space
access
DRAM access
CK
Internal
address
Address
RAS
CASxx
Miss-hit
Miss-hit
ROW
COLUMN
Wait
CS space
COLUMN
RAS assert extension
Data
Figure 9.8 Cache Fill Timing in Case of Consecutive Cache Misses from DRAM Space
(RAS Down Mode, TPC = 0, RCD = 0, No Wait)
9.4.4 Cache Hit after Cache Miss
The first cache hit after a cache miss is regarded as a cache miss, and a cache fill without idle
cycle generation is performed. The next hit operates as a cache hit.
162