PXB4219E Datasheet, PDF (99/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

FTFRS[7:0]
RFCLK
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
Depending on bit p_ces in pcfN:
0=
Structured CES: Depending on “p_tx_mfs” in
“pcfN”:
0 = Double frame mode: FTMFS is asserted every
2 frames (250 µs)
1 = CRC multiframe mode: FTMFS is asserted
every 16 frames (2 ms))
1=
Unstructured CES: Inactive level
Depending on bit “tfpp” in “opmo”:
0=
FTMFS is active low
1=
FTMFS is active high
Framer Transmit Frame Synchronization Pulse
FTFRS is asserted synchronously to the transmission of the first
bit of the first timeslot of each frame.
Reference Clock
• Reference clock for the internal clock recovery circuit
• Depending on p_rx_em in pcfN: Optional emergency clock if
no transition on FRCLK is detected within 23 CLOCK cycles.
The segmentation continues using the RFCLK divided by four,
and using the byte-pattern programmed to a_emg_bpslct in
acfg for the cell payload.
Framer Receive Interface:
FRCLKn
FRDATn
FRMFBn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
timeslot 31
Framer Transmit Interface:
FTCKOn
timeslot 0
timeslot 1
FTDATn
FTMFSn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FTFRSn
Figure 25
timeslot 31
Framer Interface in GIM E1
timeslot 0
Data Sheet
99
timeslot 1
Figime1
2003-01-20