PXB4219E Datasheet, PDF (31/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

Table 6
Pin No.
L18
W14
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Pin Descriptions
External RAM Interface (cont’d)
Symbol
Input (I) Function
Output (O)
RMADC
O
Tri
RAM Address Control
This output is asserted to indicate a valid
address on RMADR[15:0]
RMCLK
O
Tri
RAM Clock
Clock output for the external RAM. It runs at
the same frequency as CLOCK input
2.2.7 Test Interface
Table 7
Pin No.
D2
E4
C1
D1
E3
V3
A11
Y15
V18
Test Interface
Symbol
Input (I)
Output (O)
TDO
O
Tri
TDI
I
PUA
TCK
I
PUA
TMS
I
PUA
TRST
TSCEN
TSCSH
PMT
TBUS
I
PDA
I
PDA
PDA
Function
Boundary Scan Test Data Output
Boundary Scan Test Data Input
Boundary Scan Test Clock
Boundary Scan Test Mode Select
0 = normal operation
1 = Enable boundary scan test mode
Boundary Scan Test Reset
Internal Test Pins
TSCEN and TSCSH must be low for proper
operation
Internal Test Pins
00 = Intel mode
01 = prohibited
10 = prohibited
11 = Motorola Mode
Data Sheet
31
2003-01-20