PXB4219E Datasheet, PDF (131/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Memory Structure
sdt_once
crv_en
mcp_reinit
aal0
part_fill
band_width
sdt
1 = Enabled
SDT pointer appears once in 8 cell cycle
X = If [aal0] = 1 or [sdt] = 0
0 = All cells with CSI bit = 1 and even SN are supposed to contain a
P format SAR-SDU.
1 = Only the first cell with CSI bit = 1 and even SN in a cycle of 8 cells
is supposed to contain a P format SAR-SDU. (recommended for
SDT)
Data to Clock Recovery interface enable (RTS values and/or ACM buffer
filling levels) This bit may only be set for one channel per port.
X = if (pcfN[p_srts] = 0 and pcfN[p_acm] = 0) or acfg[a_crv_en] = 0
0 = Disabled
1 = Enabled
Only one channel per port may have crv_en set to 1.
Microprocessor forced reassembly buffer reinitialization
The SW should set and reset this bit to continue proper operation.
0 = Disabled
1 = Enabled
AAL0 enable
0 = Disabled (AAL1 is used)
1 = Enabled (instead of AAL1)
Partially filled cell filling level
4 to AAL0:
48 [aal0] = 1
4 to AAL1 unstructured CES:
47 [aal0] = 0, pcfN[p_ces] = 1
4 to AAL1 structured CES without CAS¹⁾:
47 [aal0] = 0, pcfN[p_ces] = 0, pcfN[p_cas] = 0
4+Cb AAL1 structured CES with CAS²⁾:
to 47 [aal0] = 0, pcfN[p_ces] = 0, pcfN[p_cas] = 1
band_width
N
(with N = number of timeslots for this channel)
X = if pcfN[p_ces] = 1
Structured Data Transfer enable
Data Sheet
131
2003-01-20