PXB4219E Datasheet, PDF (172/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Register Description
ut_par
ex_par
crv_par
oq_ovf
eq_ovf
ck_eme
Parity error on UTOPIA bus
Parity error on external RAM
In order to prevent external RAM parity errors, the external RAM should
be written completely during board initialization by the microprocessor.
0 = False
1 = True
Parity error on clock recovery interface
0 = False
1 = True
Output queue overflow
0 = False
1 = True
Error queue overflow
0 = False
1 = True
Emergency mode state change on one of the emergency mode enabled
ports (see ckmo)
0 = False
1 = True
Note: Bits 6:0 are used for tracing error events. They are set on the occurrence of an
error event and reset by a microprocessor read operation.
Bits 15:10 Bits are reset upon reading of the interrupt generating register.
Data Sheet
172
2003-01-20