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PXB4219E Datasheet, PDF (53/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Operational Description
In SDT mode, the cells are segmented when the first (multi) frame synchronization pulse
after segmentation start is received from the framer receive interface of that channel.
The resulting SC value and pointer field of the first cell transmitted will both be 0.
4.3.1.2 Segmentation
The segmentation and reassembly function can be programmed to use, alternatively to
the standard AAL type 1 SAR-PDU, a SAR-PDU that is referred to as AAL type 0 and
consists of 48 octets payload without any overhead. The selection is done by
programming the “AAL0” field in the “AAL Receive Reference Slot”.
AAL Type 0
Figure 13 shows the AAL type 0 SAR-PDU. It is possible to fill only part of the SAR-PDU
payload with User Information octets by programming field “part_fill” in the “AAL Receive
Reference Slot” of RAM1 to values smaller than 48.
AAL user info
N octets
Dummy Fill
ATM Header
5 octets
ATM-SDU = SAR-PDU
48 octets
SAR
SDU
PDU
= Segm entation & R eassem bly
= Service D ata U nit
= Protocol D ata U nit
Figure 13 SAR-PDU of AAL Type 0
ATM Layer
Aal0
AAL Type 1 SDT Structure Length
For Structured Circuit Emulation Service as defined by the ATM-Forum in “Circuit
Emulation Services Version 2.0" [10] Structured Data Transfer (SDT) is used. The
structure length used for SDT in ATM cells is:
•N
when frame-based SDT is selected
• N x 16 when CRC multiframe-based SDT is selected for E1 ports
• N x 24 when superframe-based SDT or extended superframe-based SDT is
selected for T1 ports.
The selection between frame-based or multiframe-based SDT is done by the bit
“sdt_mfs” in the “AAL Receive Reference Slot”.
4.3.1.3 Transport of the Framer Port Number
If the UTOPIA interface is configured for level 2 MPHY mode, the framer port number is
transported via the UTOPIA address bits. In UTOPIA level 1 and UTOPIA level 2 single
PHY mode the framer port number is mapped into the ATM Header (see Chapter 5.2.3).
Data Sheet
53
2003-01-20