PXB4219E Datasheet, PDF (32/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

Table 7
Pin No.
W9
Y14
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Pin Descriptions
Test Interface (cont’d)
Symbol
Input (I)
Output (O)
UTTR
I
PUA
OUTTR I
Function
Utopia TRI-STATE
0 = tristate all Utopia outputs
1 = normal operation
Output TRI-STATE
0 = tristate all outputs and disable all pull-up
and pull-down resistors
1 = normal operation
2.2.8 Miscellaneous
Table 8
Pin No.
W1
U3
L2
L3
V2
Miscellaneous
Symbol
Input (I)
Output (O)
E1/T1
I
PUA
EC
I
PUA
CLOCK I
RESET
CLK52
I
PDA
I
Function
E1 or T1 Mode Select
0 = T1 mode
1 = E1 mode
Echo Canceller Mode Select
0 = echo canceller mode
1 = standard mode
Master Clock
Used to clock the core of the device
Master Hardware Reset
Asynchronous reset of all flip-flops
51.84 MHz SRTS Reference Clock
external reference clock for SRTS. If SRTS
mode is not used, it can be connected to V_SS
Data Sheet
32
2003-01-20