PXB4219E Datasheet, PDF (145/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Memory Structure
For reading the extraction buffer, refer to Chapter 4.10.
MPADR[17:0]
27FFF_H
26060_H
2605F_H
Cell #254
·
Cell #2
2605A_H
26059_H
26042_H
26041_H
26040_H
Not Used
ATM Cell #1 Payload
ATM Cell #1 Header
The format of the ATM header entry is as follows:
RMADR[15:0]
3FFF_H
3030_H
302F_H
302D_H
302C_H
3021_H
3020_H
31
24
VCI[3:0]
PTI[2:0]
CLP
23
16
VCI[11:4]
15
8
VPI[3:0]
VCI[15:12]
7
0
GFC[3:0] or VPI[11:8]
VPI[7:4]
6.2.7 Segmentation/ATM Receive Buffers
Read/write Address 28000_H to 2FFFF_H
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 16K × 32 bits: 8 ports x 32 channels x 4 cells x 16 doublewords
Data Sheet
145
2003-01-20