PXB4219E Datasheet, PDF (11/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
List of Figures
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SRTS Jitter Tolerance in E1 Mode without Jitter Attenuator . . . . . . . 233
SRTS Jitter Tolerance in E1 Mode with Jitter Attenuator. . . . . . . . . . 234
SRTS Jitter Tolerance in T1 Mode without Jitter Attenuator . . . . . . . 235
SRTS Jitter Tolerance in T1 Mode with Jitter Attenuator . . . . . . . . . . 235
ACM Jitter Transfer in E1 Mode without Jitter Attenuator . . . . . . . . . 236
ACM Jitter Transfer in E1 Mode with Jitter Attenuator . . . . . . . . . . . . 237
ACM Jitter Transfer in T1 Mode without Jitter Attenuator . . . . . . . . . 238
ACM Jitter Transfer in T1 Mode with Jitter Attenuator . . . . . . . . . . . . 238
SRTS Jitter Transfer in E1 Mode without Jitter Attenuator . . . . . . . . 239
SRTS Jitter Transfer in E1 Mode with Jitter Attenuator . . . . . . . . . . . 240
SRTS Jitter Transfer in T1 Mode without Jitter Attenuator . . . . . . . . 241
SRTS Jitter Transfer in T1 Mode with Jitter Attenuator . . . . . . . . . . . 241
Input/Output Waveforms for AC Measurements . . . . . . . . . . . . . . . . 247
Clock and Reset Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . 247
Framer Receive Interface Timing in FAM . . . . . . . . . . . . . . . . . . . . . 248
Framer Transmit Interface Timing in FAM . . . . . . . . . . . . . . . . . . . . . 250
Framer Receive Interface Timing in GIM . . . . . . . . . . . . . . . . . . . . . . 251
Framer Transmit Interface Timing in GIM . . . . . . . . . . . . . . . . . . . . . 252
Framer Interface Timing for SYM 2.048 MHz . . . . . . . . . . . . . . . . . . 254
Framer Interface Timing in SYM 8.192 MHz . . . . . . . . . . . . . . . . . . . 255
Framer Interface Timing in EC Mode . . . . . . . . . . . . . . . . . . . . . . . . . 256
Setup and hold time definition (single- and multi PHY) . . . . . . . . . . . 257
Tri-state timing (multi-PHY, multiple devices only). . . . . . . . . . . . . . . 257
Timing of the IMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Clock Recovery Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . 261
Intel Mode Write Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 262
Intel Mode Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 263
Motorola Mode Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
RAM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Boundary-Scan Test Interface Timing Diagram . . . . . . . . . . . . . . . . . 267
Package Outline: P-BGA-256 (Plastic Metric Quad Flat Package) 273
Structure of the AAL1 SAR-PDU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Informative and Example Algorithm State Machine (Fig. III.2/I.363.1) 276
The Concept of SRTS (Fig. 5/I.363.1) . . . . . . . . . . . . . . . . . . . . . . . . 278
Generation of Residual Time Stamp (RTS) (Fig.6/ I.363.1) . . . . . . . . 279
Example Multiframe Structure for 3x64 kbit/s E1 with CAS . . . . . . . . 282
Example Multiframe Structure for 1x64 kbit/s DS1 with CAS. . . . . . . 283
Data Sheet
11
2003-01-20