PXB4219E Datasheet, PDF (103/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

FTFRS[7:0]
RFCLK
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
Framer Transmit Frame Synchronization Pulse
Unused
Reference Clock
Central framer interface clock with 8.192 MHz
RFCLK
FRDATn
FRMFB
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FTDATn
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
timeslot 31
timeslot 0
timeslot 1
Fisym8e1
Figure 27 Framer Interface in SYM8 E1
5.1.4 Echo Canceller Mode (EC)
In this mode (pin EC = 0) transmit and receive channels are synchronized.
The framer interface is clocked with an 8.192 MHz clock connected to RFCLK.
All receive channels and the channels transmitted on even ports (near-end signal with
echo) are synchronized by means of the FTFRS[0] pin. Shift exists between odd and
even FTDAT ports
FRCLK[7:0]
FRDAT[7:0]
FRMFB[7:0]
FRFRS[7:0]
FRLOS[7:0]
FTCKO[7:0]
FTDAT[7:0]
Framer Receive Clock
Unused
Framer Receive Data
FRDAT is sampled in the middle of the bit period on the falling
edge of RFCLK
Framer Receive Multiframe Begin
Unused
Framer Receive Frame Synchronization Pulse
Unused
Framer Receive Loss of Signalling
Framer Transmit Clock
Unused
Framer Transmit Data
FTDAT is clocked with the falling edge of RFCLK:
Data Sheet
103
2003-01-20