PXB4219E Datasheet, PDF (46/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Operational Description
4.2
ATM Receive Functions
For ports configured to ATM mode the following data flow is valid:
The Octet Receive Processing block is responsible for:
• Cell delineation
• HEC check: Header error detection and correction
• Cell payload de-scrambling
• Idle or Unassigned Cell Deletion
• Statistics counter event generation
• Write cells except of UDF octet to ATM Receive Buffer
The Cell Receive Processing block is responsible for:
• Read cells from ATM Receive Buffer
The ATM receive functions are controlled by the internal registers “catm”, “atmc” and
“rxid”. The features controlled by these registers are common to all ATM ports.
Some features can be controlled per port. They were configured by programming the
port specific “ATM Receive Reference Slot” in the internal configuration RAM.
4.2.1 Operation
4.2.1.1 Cell Delineation
The cell delineation algorithm is implemented according to the ITU-T Recommendation
I.432.1 [33].
To support detection of “Out of Cell Delineation” (OCD) anomalies and “Loss of Cell
Delineation” (LCD) defect, the IWE8 generates an interrupt in eis4 (Chapter 7.22)
whenever the SYNC state is left or entered. The generation of interrupts is controllable
on a per port basis through fields in the “ATM Receive Reference Slot” of RAM1
(Chapter 6.1.1.1). It is also possible to see the current state of the cell delineation FSM
(Finite State Machine) in the Cell Delineation FSM Status Register (“cdfs”, see
Chapter 7.15).
The software can then start a timer (e.g. timer_set_1 provided by the IWE8) to establish
the LCD defect state.
As octet boundaries are available within the receive physical layer prior to cell
delineation, the cell delineation process is performed octet by octet in the HUNT state.
As long as the cell delineation is not in the SYNC state, received octets are discarded.
The ALPHA and DELTA parameters, which influence the robustness of the algorithm
against false misalignment due to bit errors (ALPHA) and false delineation in the re
synchronization process (DELTA), are programmable to values between 0 and 15 in the
ATM Control Register (atmc, see Chapter 7.8), These settings are common for all ATM
ports. ITU-T I.432.1 [33] recommends:
Data Sheet
46
2003-01-20