PXB4219E Datasheet, PDF (41/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Functional Description
Table 11
Block
CV
RB
CK
JT
ICRC
External
RAM
Functions of IWE8 Blocks (cont’d)
Functions
External Clock Recovery interface
• Generation of serial communication frames to external clock recovery
circuit, containing RTS values and or ACM buffer filling
• Generation of synchronization for RTS generation by external clock
recovery circuit.
• Reception of frames with RTS values from external clock recovery circuit
RTS Buffer
• Buffer for 2 incoming RTS values per port
Clock & Reset
• Clock distribution
• Reset control
JTAG interface
• Boundary Scan register
• TAP controller
Internal Clock Recovery Circuit
• Synchronous Residual Time Stamp SRTS
• Adaptive Clock Method ACM
ATM Transmit Buffer
• Compensate packetization delay on the PDH interface.
• Maximum size of 256 ATM cells per port.
• Maximum size of 64 octets per ATM cell.
ATM Receive Buffer
• Maximum size of 16 ATM cells per port.
• Maximum size of 64 octets per ATM cell.
Segmentation Buffer
• Compensate segmentation delay in the ATM network.
• 1024 bytes per port (unstructured CES)
• 256 bytes per timeslot (structured CES)
Reassembly Buffer
• Compensate the Cell Delay Variation (CDV) of the ATM network.
• 512 bytes per timeslot. (structured CES)
Data Sheet
41
2003-01-20